Final Report of BeJamDetect Project 
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Figure 4-3: Measured reception characteristics of antenna array elements at L1/E’ 
The hardware platform used by the Demonstrator 2 is the miniaturised GALANT receiver (see Figure 
4-5). It is based on the use of a combination of a commercial base-board with a system-on-module 
‚SoM) board of type PicoZed AES Z7PZ-7Z030-SOM-I-G. These two components are shown in 
Cigure 4-4 where the SoM in black colour is mounted on the top of the base-board in green. The 
50M is equipped with a Xilinx Zynq Z7030 system-on-chip (SoC), a combination of FPGA and CPU, 
which is designed as a common integrated circuit. Such a SoC allows fast data exchange between 
the programmable logic of the FPGA and a processor for generic-type calculations. The SoC 
topology is particularly advantageous for systems with antenna arrays: the necessary parallel signal 
orocessing of all channels in real time can be well realized in the FPGA. The software-side processing 
of the received signals then takes place on the CPU. In the case of a GNSS receiver, the software 
includes in particular the calculation of the PVT solution, but also algorithms for position estimation 
and communication with the user. 
Figure 4-4: Base-board and SoM of miniaturised GALANT platform 
Title: Final Report 
Version: 1.0 
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